Integrated circuits find application in many of today's consumer electronics, such as cell phones, video cameras, portable music players, printers, computers, location based devices, etc. Integrated circuits may include a combination of active devices, passive devices and their interconnections.
The ever increasing demand for higher density and higher performance integrated circuits has driven the market to seek the production of sub-micron sized low resistance metallization patterns, such as a copper interconnect. Unfortunately, one of the major challenges of copper metallurgy is that it cannot be easily patterned by regular plasma etching techniques. To overcome this problem, the circuit designers have implemented damascene processes that form the necessary copper vias and interconnects within an integrated circuit.
The damascene process typically starts with deposition of a dielectric material that is patterned and etched to form holes or trenches within the dielectric. These holes or trenches are then filled with a blanket deposit of metal, which is then planarized down to the dielectric to define the metal interconnects within the dielectric. Typically, the excess metal material formed over the dielectric is removed by a chemical mechanical planarization (CMP) process. Unfortunately, CMP processes and photoresist patterning can be damaging to soft, low-modulus, and porous low-K dielectric layers. Thus, many previous methodologies have employed the extra step of forming a hard mask layer to protect these low-K dielectric layers, but this can raise the overall effective dielectric constant (K) of the insulating material. Any increase in the effective dielectric constant (K) defeats the purpose of using the low-K dielectric layer in the first place, which is to reduce the capacitance of the layer to better isolate the metal structures in the layer.
Other attempts to improve copper interconnect reliability have focused on copper surface passivation. This technique typically employs a chemically-vapor deposited (CVD) thin dielectric layer atop of a polished copper interconnect. Generally, the thin dielectric may include silicon nitride or nitrogen-doped silicon carbide, wherein nitrogen-doped silicon carbide has replaced silicon nitride since 90 nm onwards due to capacitance requirements and process control. Unfortunately, CVD passivation of copper interconnects has failed to provide sufficient reliability margin as the technology nodes continue to decrease.
Thus, a need still remains for a reliable integrated circuit system, method of fabrication, and device design, wherein the integrated circuit system exhibits improved metal interconnect reliability. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.